嵌入式培训

 
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北京报名热线:010-51292078
深圳报名热线:4008699035
南京报名热线:4008699035
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成都报名热线:4008699035
广州报名热线:
4008699035
西安报名热线:
029-86699670
曙海研发与生产请参见网址:
www.shanghai66.cn
全英文授课课程(Training in English)
  首 页   课程介绍   培训报名  企业培训   付款方式   讲师介绍   学员评价   关于我们   联系我们  承接项目 开发板商城  学院论坛
        PrimeRail培训
  培养对象
  1.理工科背景,有志于数字集成电路设计工作的学生和转行人员;
  2.需要充电,提升技术水平和熟悉设计流程的在职人员;
  3.集成电路设计企业的员工内训。
   入学要求

        学员学习本课程应具备下列基础知识:
        ◆电路系统的基本概念。

   班级规模及环境--热线:4008699035 手机:15921673576( 微信同号)
       坚持小班授课,为保证培训效果,增加互动环节,每期人数限3到5人。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山学院/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦 【广州分部】:广粮大厦 【西安分部】:协同大厦
最近开课时间(周末班/连续班/晚班):
PrimeRail培训开班时间:即将开课,详情请咨询客服!
   实验设备
     ☆资深工程师授课

        
        ☆注重质量
        ☆边讲边练

        ☆合格学员免费推荐工作

        ☆合格学员免费颁发相关工程师等资格证书,提升您的职业资质

        专注高端培训15年,曙海提供的证书得到本行业的广泛认可,学员的能力
        得到大家的认同,受到用人单位的广泛赞誉。

        ★实验设备请点击这儿查看★
   最新优惠
       ◆在读学生凭学生证,可优惠500元。
   质量保障

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、课程完成后,授课老师留给学员手机和Email,保障培训效果,免费提供半年的技术支持。
        3、培训合格学员可享受免费推荐就业机会。

 
                PrimeRail培训

第一阶段

ObjectivesAt the end of this workshop the student should be able to:
  • Set up and perform Power/Ground (PG) reliability analysis for checking Static and Dynamic Voltage Drop and Electromigration (EM) potential violations
  • Explanation of and/or set up the phases of Dynamic analysis of PrimeRail that involve the following:
    • Library Characterization
    • Data preparation
    • Power Analysis
    • PG Parasitic (RC) Extraction
    • Dynamic (Transient) Rail Analysis
    • Violation Viewing, Reporting and Correction
    • What-if Analysis ? Package parasitics and Decap insertion
    • Voltage Drop Derated Timing Analysis
    • Accurate Hard Macro Modeling
    • Power Management( power switch) Cell handling
  • Set up PG analysis for hierarchical and top-level
  • Use the PrimeRail graphical user interface (GUI) for the PG rail analysis, including what-if analysis
Audience Profile
Design, verification or CAD engineers who perform power/ground interconnect reliability analysis at the "Block" or "Full-Chip" levels. This covers a wide spectrum of designs of digital, memory, and analog/mixed signal.Prerequisites
Experience in the following areas is recommended to gain the most value from the workshop content:
  • Physical layout
  • Physical extraction
  • Power simulation
Static Analysis
  • Introduction to Rail Analysis - requirements, capabilities and database preparation
  • Power and Timing Model creation
  • Power supply, net switching and Transition Time inputs
  • Power and Rail Analysis
  • Mapping, reporting, querying and what-if Analysis
  • Integrated Flows - Hardmacro modeling, Power gating and Voltage derated timing analysis
第二阶段
Dynamic ( Transient) Analysis
  • Introduction, database requirements and flows
  • Library Characterization and LSF
  • Cell-Level Dynamic Analysis-PP Run
  • Cell-Level Dynamic Analysis-Transient Analysis
  • What-if Analysis ? Package Parasitics and Decap Insertion
  • Mapping, waveform viewing, reporting and querying
  • Tx-Level Dynamic Analysis-Data Preparation
  • Tx-Level Dynamic Analysis
  • Tx-Level Signal EM Analysis
  • Macro Modeling - Memory, Analog, custom or Hardmacro blocks